#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <asm/mach/map.h>
#include <mach/pmu.h>
#include <mach/clock.h>
#include <mach/board_config.h>

/*
 * external oscillator
 * fixed to 24M
 */
static struct fh_clk osc_clk = {
	.name               = "osc_clk",
	.frequency          = OSC_FREQUENCY,
	.flag               = CLOCK_FIXED|CLOCK_NOGATE,
};

static struct fh_clk pll0_rclk = {
	.name               = "pll0_rclk",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_DDR_PLL0_CTRL0,
	.en_reg_offset      = REG_DDR_PLL0_CTRL1,
	.en_reg_mask        = 0xf000,
};

static struct fh_clk pll0_pclk = {
	.name               = "pll0_pclk",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_DDR_PLL0_CTRL0,
	.en_reg_offset      = REG_DDR_PLL0_CTRL1,
	.en_reg_mask        = 0xf00,
};

static struct fh_clk pll1_rclk = {
	.name               = "pll1_rclk",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL1_CTRL0,
	.en_reg_offset      = REG_PMU_PLL1_CTRL1,
	.en_reg_mask        = 0xf000,
};

static struct fh_clk pll1_pclk = {
	.name               = "pll1_pclk",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL1_CTRL0,
	.en_reg_offset      = REG_PMU_PLL1_CTRL1,
	.en_reg_mask        = 0xf00,
};

static struct fh_clk pll2_rclk = {
	.name               = "pll2_rclk",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL2_CTRL0,
	.en_reg_offset      = REG_PMU_PLL2_CTRL1,
	.en_reg_mask        = 0xf000,
};

static struct fh_clk pll2_pclk = {
	.name               = "pll2_pclk",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL2_CTRL0,
	.en_reg_offset      = REG_PMU_PLL2_CTRL1,
	.en_reg_mask        = 0xf00,
};

static struct fh_clk pll3_rclk = {
	.name               = "pll3_rclk",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL3_CTRL0,
	.en_reg_offset      = REG_PMU_PLL3_CTRL1,
	.en_reg_mask        = 0xf000,
};

static struct fh_clk pll3_pclk = {
	.name               = "pll3_pclk",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_PLL3_CTRL0,
	.en_reg_offset      = REG_PMU_PLL3_CTRL1,
	.en_reg_mask        = 0xf00,
};

static struct fh_clk pll4_rclk = {
	.name               = "pll4_rclk",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL4_CTRL0,
	.en_reg_offset      = REG_PMU_PLL4_CTRL1,
	.en_reg_mask        = 0xf000,
};

static struct fh_clk pll4_pclk = {
	.name               = "pll4_pclk",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_PLL4_CTRL0,
	.en_reg_offset      = REG_PMU_PLL4_CTRL1,
	.en_reg_mask        = 0xf00,
};

static struct fh_clk pll1_div3_pclk = {
	.name               = "pll1_div3_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll1_pclk},
	.prediv             = 3,
};

static struct fh_clk pll1_div2_pclk = {
	.name               = "pll1_div2_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll1_pclk},
	.prediv             = 2,
};

static struct fh_clk pll1_div4_pclk = {
	.name               = "pll1_div4_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll1_pclk},
	.prediv             = 4,
};

static struct fh_clk pll1_div8_pclk = {
	.name               = "pll1_div8_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll1_pclk},
	.prediv             = 8,
};

static struct fh_clk pll1_div16_pclk = {
	.name               = "pll1_div16_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll1_pclk},
	.prediv             = 16,
};

static struct fh_clk pll1_div30_pclk = {
	.name               = "pll1_div30_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll1_pclk},
	.prediv             = 30,
};

static struct fh_clk pll2_div2_pclk = {
	.name               = "pll2_div2_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 2,
};

static struct fh_clk pll2_div3_pclk = {
	.name               = "pll2_div3_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 3,
};

static struct fh_clk pll2_div4_pclk = {
	.name               = "pll2_div4_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 4,
};

static struct fh_clk pll2_div5_pclk = {
	.name               = "pll2_div5_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 5,
};

static struct fh_clk pll2_div6_pclk = {
	.name               = "pll2_div6_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 6,
};

static struct fh_clk pll2_div7_pclk = {
	.name               = "pll2_div7_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 7,
};

static struct fh_clk pll2_div8_pclk = {
	.name               = "pll2_div8_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 8,
};

static struct fh_clk pll2_div9_pclk = {
	.name               = "pll2_div9_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 9,
};

static struct fh_clk pll2_div10_pclk = {
	.name               = "pll2_div10_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 10,
};

static struct fh_clk pll2_div12_pclk = {
	.name               = "pll2_div12_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 12,
};

static struct fh_clk pll2_div15_pclk = {
	.name               = "pll2_div15_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 15,
};

static struct fh_clk pll2_div20_pclk = {
	.name               = "pll2_div20_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 20,
};

static struct fh_clk pll2_div24_pclk = {
	.name               = "pll2_div24_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 24,
};

static struct fh_clk pll2_div30_pclk = {
	.name               = "pll2_div30_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 30,
};

static struct fh_clk pll2_div60_pclk = {
	.name               = "pll2_div60_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_pclk},
	.prediv             = 60,
};

static struct fh_clk pll2_div3_rclk = {
	.name               = "pll2_div3_rclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll2_rclk},
	.prediv             = 3,
};


static struct fh_clk pll3_div3_pclk = {
	.name               = "pll3_div3_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 3,
};

static struct fh_clk pll3_div6_pclk = {
	.name               = "pll3_div6_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 6,
};

static struct fh_clk pll3_div2_pclk = {
	.name               = "pll3_div2_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 2,
};

static struct fh_clk pll3_div4_pclk = {
	.name               = "pll3_div4_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 4,
};

static struct fh_clk pll3_div5_pclk = {
	.name               = "pll3_div5_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 5,
};

static struct fh_clk pll3_div7_pclk = {
	.name               = "pll3_div7_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 7,
};

static struct fh_clk pll3_div8_pclk = {
	.name               = "pll3_div8_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 8,
};

static struct fh_clk pll3_div16_pclk = {
	.name               = "pll3_div16_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 16,
};

static struct fh_clk pll3_div32_pclk = {
	.name               = "pll3_div32_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 32,
};

static struct fh_clk pll3_div44_pclk = {
	.name               = "pll3_div44_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll3_pclk},
	.prediv             = 44,
};


static struct fh_clk pll4_div2_pclk = {
	.name               = "pll4_div2_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 2,
};

static struct fh_clk pll4_div24_pclk = {
	.name               = "pll4_div24_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 24,
};

static struct fh_clk pll4_div3_pclk = {
	.name               = "pll4_div3_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 3,
};


static struct fh_clk pll4_div4_pclk = {
	.name               = "pll4_div4_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 4,
};

static struct fh_clk pll4_div5_pclk = {
	.name               = "pll4_div5_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 5,
};

static struct fh_clk pll4_div6_pclk = {
	.name               = "pll4_div6_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 6,
};

static struct fh_clk pll4_div7_pclk = {
	.name               = "pll4_div7_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 7,
};

static struct fh_clk pll4_div8_pclk = {
	.name               = "pll4_div8_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 8,
};

static struct fh_clk pll4_div9_pclk = {
	.name               = "pll4_div9_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 9,
};

static struct fh_clk pll4_div32_pclk = {
	.name               = "pll4_div32_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 32,
};

static struct fh_clk pll4_div44_pclk = {
	.name               = "pll4_div44_pclk",
	.flag               = CLOCK_NODIV|CLOCK_NOGATE|CLOCK_HIDE,
	.parent             = {&pll4_pclk},
	.prediv             = 44,
};
#if 1
static struct fh_clk ddr_clk = {
	.name               = "ddr_clk",
	.flag				= CLOCK_NODIV,
	.prediv             = 2,
	.parent             = {&pll0_pclk},
	.en_reg_offset		= REG_DDR_CLK_CTRL,
	.en_reg_mask		= 0x8,
};
static struct fh_clk arm_clk = {
	.name               = "arm_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk, &pll1_pclk, &pll2_div2_pclk,
		&pll3_div2_pclk, &pll2_div3_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x7,
};
static struct fh_clk arc_clk = {
	.name               = "arc_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll3_div2_pclk, &pll2_div3_pclk,
		&pll3_div3_pclk, &pll2_div5_pclk, &pll2_div6_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x38,
	.en_reg_offset		= REG_PMU_CPU_GATE,
	.en_reg_mask		= 0x2,
};
static struct fh_clk sys_ahb_clk = {
	.name               = "sys_ahb_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk, &pll2_div7_pclk,
		&pll2_div10_pclk, &pll2_div15_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0xc0,
};
/*hclk*/
static struct fh_clk ahb_clk = {
	.name               = "ahb_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk, &pll2_div7_pclk,
		&pll2_div10_pclk, &pll2_div15_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x300,
};

static struct fh_clk isp_aclk = {
	.name               = "isp_aclk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll4_div4_pclk, &pll2_div5_pclk,
		&pll2_div6_pclk, &pll1_div4_pclk, &pll3_div6_pclk,
		&pll2_div10_pclk, &pll2_div12_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x7000,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x1,
};
static struct fh_clk isp_hclk = {
	.name               = "isp_hclk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &pll2_div7_pclk,
		&pll2_div10_pclk, &pll2_div15_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x18000,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x10000,
};

static struct fh_clk vicap_clk = {
	.name               = "vicap_clk",
	.flag				= CLOCK_NODIV,
	.parent             = {&isp_aclk},
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x2,
};

static struct fh_clk vicap_hclk = {
	.name               = "vicap_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x20000,
};




static struct fh_clk vpu_clk = {
	.name               = "vpu_clk",
	.flag				= CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.prediv             = 1,
	.parent             = {&pll2_div3_pclk, &pll1_div2_pclk,
					&pll3_div3_pclk, &pll2_div5_pclk,
					&pll2_div6_pclk, &pll3_div6_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL2,
	.sel_reg_mask       = 0x70000000,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x10,
};
static struct fh_clk vpu_hclk = {
	.name               = "vpu_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x80000,
};

static struct fh_clk lut2d_clk = {
	.name               = "lut2d_clk",
	.flag				= CLOCK_NODIV,
	.parent             = {&vpu_clk},
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x4,
};

static struct fh_clk lut2d_hclk = {
	.name               = "lut2d_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x80000,
};


static struct fh_clk vou_clk = {
	.name               = "vou_clk",
	.flag				= CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.prediv             = 1,
	.parent             = {&pll2_div5_pclk, &pll2_div6_pclk,
		&pll2_div8_pclk, &pll2_div10_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0xc00,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x20,
};

static struct fh_clk vou_hclk = {
	.name               = "vou_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x100000,
};

static struct fh_clk jpeg_clk = {
	.name               = "jpeg_clk",
	.flag				= CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.prediv             = 1,
	.parent             = {&pll3_div3_pclk, &pll2_div5_pclk,
		&pll2_div6_pclk, &pll3_div6_pclk,
		&pll2_div10_pclk, &pll2_div15_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0xe0000,
	.en_reg_offset		= REG_PMU_VEU_GATE,
	.en_reg_mask		= 0x2,
};
static struct fh_clk jpeg_hclk = {
	.name               = "jpeg_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_VEU_GATE,
	.en_reg_mask		= 0x20000,
};
static struct fh_clk jpeg_lpbuf_clk = {
	.name               = "jpeg_lpbuf_clk",
	.flag				= CLOCK_NODIV,
	.parent             = {&jpeg_clk},
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_VEU_GATE,
	.en_reg_mask		= 0x8,
};
static struct fh_clk jpeg_lpbuf_hclk = {
	.name               = "jpeg_lpbuf_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_VEU_GATE,
	.en_reg_mask		= 0x80000,
};

static struct fh_clk veu_clk = {
	.name               = "veu_clk",
	.flag				= CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.prediv             = 1,
	.parent             = {&pll4_div2_pclk, &pll3_div2_pclk,
					&pll2_div3_pclk, &pll4_div3_pclk,
					&pll3_div3_pclk, &pll2_div5_pclk,
					&pll2_div6_pclk, &pll2_div7_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x700000,
	.en_reg_offset		= REG_PMU_VEU_GATE,
	.en_reg_mask		= 0x1,
};

static struct fh_clk veu_hclk = {
	.name               = "veu_hclk",
	.flag				= CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &pll3_div3_pclk,
					&pll2_div5_pclk, &pll2_div7_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x3000000,
	.en_reg_offset		= REG_PMU_VEU_GATE,
	.en_reg_mask		= 0x10000,
};

static struct fh_clk veu_lpbuf_clk = {
	.name               = "veu_lpbuf_clk",
	.flag				= CLOCK_NODIV,
	.parent             = {&veu_clk},
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_VEU_GATE,
	.en_reg_mask		= 0x4,
};
static struct fh_clk veu_lpbuf_hclk = {
	.name               = "veu_lpbuf_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_VEU_GATE,
	.en_reg_mask		= 0x40000,
};

static struct fh_clk nn_clk = {
	.name               = "nn_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll3_div2_pclk, &pll2_div3_pclk,
					&pll3_div3_pclk, &pll2_div5_pclk,
					&pll4_div7_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x1c000000,
};

static struct fh_clk nn_hclk = {
	.name               = "nn_hclk",
	.flag               = CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_NN_GATE,
	.en_reg_mask        = 0x10000,

};


static struct fh_clk bgm_clk = {
	.name               = "bgm_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_div6_pclk, &pll2_div8_pclk,
					&pll2_div10_pclk, &pll2_div12_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x18,
	.en_reg_offset		= REG_PMU_NN_GATE,
	.en_reg_mask		= 0x2,
};
static struct fh_clk bgm_hclk = {
	.name               = "bgm_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_NN_GATE,
	.en_reg_mask		= 0x20000,
};

static struct fh_clk vgs_clk = {
	.name               = "vgs_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_div3_pclk, &pll1_div2_pclk,
					&pll3_div3_pclk, &pll4_div4_pclk,
					&pll2_div5_pclk, &pll2_div6_pclk,
					&pll2_div10_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x7,
	.en_reg_offset		= REG_PMU_NN_GATE,
	.en_reg_mask		= 0x4,
};

static struct fh_clk vgs_hclk = {
	.name               = "vgs_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_NN_GATE,
	.en_reg_mask		= 0x40000,
};
static struct fh_clk nn_sys_clk = {
	.name               = "nn_sys_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll3_div2_pclk, &pll2_div3_pclk,
					&pll3_div3_pclk, &pll2_div5_pclk,
					&pll4_div7_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL2,
	.sel_reg_mask       = 0xe000000,
};

static struct fh_clk nn_sys_hclk = {
	.name               = "nn_sys_hclk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk, &pll2_div7_pclk,
					&pll2_div10_pclk, &pll2_div15_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL0,
	.sel_reg_mask       = 0x60000000,
};

static struct fh_clk sdc0_clk = {
	.name               = "sdc0_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_rclk, &pll2_div15_pclk},
	.prediv             = 4,
	.sel_reg_offset     = REG_PMU_CLK_SEL3,
	.sel_reg_mask       = 0x1,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x1,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x8000,
};

static struct fh_clk sdc1_clk = {
	.name               = "sdc1_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_rclk, &pll2_div15_pclk},
	.prediv             = 4,
	.sel_reg_offset     = REG_PMU_CLK_SEL3,
	.sel_reg_mask       = 0x10,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x2,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x10000,
};

static struct fh_clk cis_clk_out = {
	.name               = "cis_clk_out",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &pll3_div32_pclk, &pll3_div44_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x60,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x4,
};

static struct fh_clk cis1_clk_out = {
	.name               = "cis1_clk_out",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &pll3_div32_pclk, &pll3_div44_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x180,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x8,
};

static struct fh_clk mipi0_cfg_clk = {
	.name               = "mipi0_cfg_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_div12_pclk, &pll2_div15_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x200,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x10,
};

static struct fh_clk mipi1_cfg_clk = {
	.name               = "mipi1_cfg_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_div12_pclk, &pll2_div15_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x400,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x20,
};


static struct fh_clk ave_clk = {
	.name               = "ave_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll1_div3_pclk, &pll3_div4_pclk,
				&pll1_div4_pclk, &pll3_div8_pclk,
				&pll1_div8_pclk, &pll3_div16_pclk,
				&pll1_div16_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0xe000,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x40,
	.def_rate			= 148500000,
};
static struct fh_clk ave_hclk = {
	.name               = "ave_hclk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_ISP_GATE,
	.en_reg_mask		= 0x200000,
};

static struct fh_clk dv_clk = {
	.name               = "dv_clk",
	.flag				= CLOCK_NODIV,
	.parent             = {&ave_clk},
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x80,
};


static struct fh_clk spi0_clk = {
	.name               = "spi0_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_rclk, &pll3_div6_pclk,
				&pll2_div8_pclk, &pll2_div15_pclk,
				&pll2_div30_pclk, &pll2_div60_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL2,
	.sel_reg_mask       = 0x7,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x100,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x20000,
};

static struct fh_clk spi1_clk = {
	.name               = "spi1_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_div15_pclk, &pll2_div20_pclk,
					&pll2_div24_pclk, &pll2_div30_pclk,
					&pll2_div60_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL2,
	.sel_reg_mask       = 0x38,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x200,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x40000,
};

static struct fh_clk spi2_clk = {
	.name               = "spi2_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_div15_pclk, &pll2_div20_pclk,
					&pll2_div24_pclk, &pll2_div30_pclk,
					&pll2_div60_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL2,
	.sel_reg_mask       = 0x1c0,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x400,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x80000,
};
static struct fh_clk spi3_clk = {
	.name               = "spi3_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_div15_pclk, &pll2_div20_pclk,
					&pll2_div24_pclk, &pll2_div30_pclk,
					&pll2_div60_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL2,
	.sel_reg_mask       = 0x700000,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x80,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x4000000,
};

static struct fh_clk hash_clk = {
	.name               = "hash_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&pll2_div6_pclk, &pll2_div7_pclk,
					&pll2_div10_pclk, &pll2_div15_pclk},
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL2,
	.sel_reg_mask       = 0x600,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x40,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x2000000,
};

static struct fh_clk i2c0_clk = {
	.name               = "i2c0_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0x3f,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x800,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x1,
};

static struct fh_clk i2c1_clk = {
	.name               = "i2c1_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xfc0,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x1000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x2,
};

static struct fh_clk i2c2_clk = {
	.name               = "i2c2_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0x3f000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x2000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x4,
};

static struct fh_clk i2c3_clk = {
	.name               = "i2c3_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0xfc0000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x4000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x8,
};
static struct fh_clk i2c4_clk = {
	.name               = "i2c4_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV0,
	.div_reg_mask       = 0x3f000000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x8000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x10,
};


static struct fh_clk pwm_clk = {
	.name               = "pwm_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0xff,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x10000,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x400000,
};

static struct fh_clk uart0_clk = {
	.name               = "uart0_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0x3f00,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x20000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x20,
	.def_rate			= 16666666,
};

static struct fh_clk uart1_clk = {
	.name               = "uart1_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0xfc000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x40000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x40,
	.def_rate			= 16666666,
};
static struct fh_clk uart2_clk = {
	.name               = "uart2_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0x3f00000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x80000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x80,
	.def_rate			= 16666666,
};

static struct fh_clk uart3_clk = {
	.name               = "uart3_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV1,
	.div_reg_mask       = 0xfc000000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x100000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x100,
	.def_rate			= 16666666,
};

static struct fh_clk stm0_clk = {
	.name               = "stm0_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV2,
	.div_reg_mask       = 0x3f,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x200000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x800,
};

static struct fh_clk stm1_clk = {
	.name               = "stm1_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV2,
	.div_reg_mask       = 0xfc0,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x400000,
	.en_reg_offset1		= REG_PMU_CLK_GATE2,
	.en_reg_mask1		= 0x1000,
};

static struct fh_clk pts_clk = {
	.name               = "pts_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV2,
	.div_reg_mask       = 0x1ff000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x800000,
};

static struct fh_clk efuse_clk = {
	.name               = "efuse_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV2,
	.div_reg_mask       = 0x7e00000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x1000000,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x800000,
};

static struct fh_clk tmr0_clk = {
	.name               = "tmr0_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV6,
	.div_reg_mask       = 0xff,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x2000000,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x400,
};

static struct fh_clk tmr1_clk = {
	.name               = "tmr1_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV6,
	.div_reg_mask       = 0xff00,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x80000000,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x800,
};

static struct fh_clk sadc_clk = {
	.name               = "sadc_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV3,
	.div_reg_mask       = 0x1ff00,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x4000000,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x1000,
};

static struct fh_clk wdt_clk = {
	.name               = "wdt_clk",
	.parent             = {&ahb_clk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV6,
	.div_reg_mask       = 0xff0000,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x100000,
};

static struct fh_clk gpio0_db_clk = {
	.name               = "gpio0_db_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV3,
	.div_reg_mask       = 0x7ffe0000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x8000000,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x2000,
};

static struct fh_clk gpio1_db_clk = {
	.name               = "gpio1_db_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV4,
	.div_reg_mask       = 0x3fff,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x10000000,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x4000,
};
static struct fh_clk gpio2_db_clk = {
	.name               = "gpio2_db_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV4,
	.div_reg_mask       = 0xfffc000,
	.en_reg_offset		= REG_PMU_CLK_GATE0,
	.en_reg_mask		= 0x20000000,
	.en_reg_offset1		= REG_PMU_CLK_GATE1,
	.en_reg_mask1		= 0x8000,
};

static struct fh_clk eth_clk = {
	.name               = "eth_clk",
	.parent             = {&pll2_div15_pclk},
	.prediv             = 1,
	.div_reg_offset     = REG_PMU_CLK_DIV4,
	.div_reg_mask       = 0xf0000000,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x1,
};

static struct fh_clk rgmii_tx_gate = {
	.name               = "rgmii_tx_clk",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x2,
};
static struct fh_clk eth_rmii_gate = {
	.name               = "eth_rmii_gate",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x4,
};

static struct fh_clk ephy_clk_gate = {
	.name               = "ephy_clk_gate",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= 0x8,
};

static struct fh_clk ac_clk = {
	.name               = "ac_clk",
	.flag				= CLOCK_NODIV,
	.parent             = {&osc_clk},
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_CLK_GATE1,
	.en_reg_mask        = 0x10,

};

static struct fh_clk i2s_clk = {
	.name               = "i2s_clk",
	.flag				= CLOCK_NODIV,
	.parent             = {&ac_clk},
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_CLK_GATE1,
	.en_reg_mask        = 0x20,
};

static struct fh_clk acodec_pclk_gate = {
	.name               = "acodec_pclk_gate",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= REG_PMU_CLK_GATE2,
	.en_reg_mask		= 0x200,
};

static struct fh_clk ephy_pclk_gate = {
	.name               = "ephy_pclk_gate",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_CLK_GATE2,
	.en_reg_mask        = 0x400,
};

static struct fh_clk tzpc_pclk_gate = {
	.name               = "tzpc_pclk_gate",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_CLK_GATE2,
	.en_reg_mask        = 0x2000,
};

static struct fh_clk mipi0_pclk_gate = {
	.name               = "mipi0_pclk_gate",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_ISP_GATE,
	.en_reg_mask        = 0x400000,
};

static struct fh_clk mipi1_pclk_gate = {
	.name               = "mipi1_pclk_gate",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_ISP_GATE,
	.en_reg_mask        = 0x800000,
};

static struct fh_clk mipi2_pclk_gate = {
	.name               = "mipi2_pclk_gate",
	.flag				= CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset      = REG_PMU_ISP_GATE,
	.en_reg_mask        = 0x1000000,
};


static struct fh_clk sdc0_clk_sample = {
	.name               = "sdc0_clk_sample",
	.parent             = {&sdc0_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x700000,
};

static struct fh_clk sdc0_clk_drv = {
	.name               = "sdc0_clk_drv",
	.parent             = {&sdc0_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x70000,
};

static struct fh_clk sdc1_clk_sample = {
	.name               = "sdc1_clk_sample",
	.parent             = {&sdc1_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x70000000,
};

static struct fh_clk sdc1_clk_drv = {
	.name               = "sdc1_clk_drv",
	.parent             = {&sdc1_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = REG_PMU_CLK_SEL1,
	.sel_reg_mask       = 0x7000000,
};

static struct fh_clk rtc_pclk_gate = {
	.name               = "rtc_pclk_gate",
	.flag				= CLOCK_NORESET | CLOCK_NODIV,
	.en_reg_offset		= REG_PMU_CLK_GATE1,
	.en_reg_mask		= BIT(21),
};

#endif
struct fh_clk *fh_clks[] = {
#if 1
	&osc_clk,
	&pll0_rclk,
	&pll0_pclk,
	&pll1_rclk,
	&pll1_pclk,
	&pll2_rclk,
	&pll2_pclk,
	&pll3_rclk,
	&pll3_pclk,
	&pll4_rclk,
	&pll4_pclk,
	&pll1_div3_pclk,
	&pll1_div2_pclk,
	&pll1_div4_pclk,
	&pll1_div8_pclk,
	&pll1_div16_pclk,
	&pll1_div30_pclk,
	&pll2_div2_pclk,
	&pll2_div3_pclk,
	&pll2_div4_pclk,
	&pll2_div5_pclk,
	&pll2_div6_pclk,
	&pll2_div7_pclk,
	&pll2_div8_pclk,
	&pll2_div9_pclk,
	&pll2_div10_pclk,
	&pll2_div12_pclk,
	&pll2_div15_pclk,
	&pll2_div20_pclk,
	&pll2_div24_pclk,
	&pll2_div30_pclk,
	&pll2_div60_pclk,
	&pll2_div3_rclk,
	&pll3_div2_pclk,
	&pll3_div3_pclk,
	&pll3_div6_pclk,
	&pll3_div4_pclk,
	&pll3_div5_pclk,
	&pll3_div7_pclk,
	&pll3_div8_pclk,
	&pll3_div16_pclk,
	&pll3_div32_pclk,
	&pll3_div44_pclk,
	&pll4_div2_pclk,
	&pll4_div24_pclk,
	&pll4_div3_pclk,
	&pll4_div4_pclk,
	&pll4_div5_pclk,
	&pll4_div6_pclk,
	&pll4_div7_pclk,
	&pll4_div8_pclk,
	&pll4_div9_pclk,
	&pll4_div32_pclk,
	&pll4_div44_pclk,
#endif
#if 1
	&ddr_clk,
	&arm_clk,
	&arc_clk,
	&sys_ahb_clk,
	&ahb_clk,
	&isp_aclk,
	&isp_hclk,
	&vicap_clk,
	&vicap_hclk,
	&lut2d_clk,
	&lut2d_hclk,
	&vpu_clk,
	&vpu_hclk,
	&vou_clk,
	&vou_hclk,
	&jpeg_clk,
	&jpeg_hclk,
	&jpeg_lpbuf_clk,
	&jpeg_lpbuf_hclk,
	&veu_clk,
	&veu_hclk,
	&veu_lpbuf_clk,
	&veu_lpbuf_hclk,
	&nn_clk,
	&nn_hclk,
	&bgm_clk,
	&bgm_hclk,
	&vgs_clk,
	&vgs_hclk,
	&nn_sys_clk,
	&nn_sys_hclk,
	&sdc0_clk,
	&sdc1_clk,
	&cis_clk_out,
	&cis1_clk_out,
	&mipi0_cfg_clk,
	&mipi1_cfg_clk,
	&ave_clk,
	&ave_hclk,
	&dv_clk,
	&spi0_clk,
	&spi1_clk,
	&spi2_clk,
	&spi3_clk,
	&hash_clk,
	&i2c0_clk,
	&i2c1_clk,
	&i2c2_clk,
	&i2c3_clk,
	&i2c4_clk,
	&pwm_clk,
	&uart0_clk,
	&uart1_clk,
	&uart2_clk,
	&uart3_clk,
	&stm0_clk,
	&stm1_clk,
	&pts_clk,
	&efuse_clk,
	&tmr0_clk,
	&tmr1_clk,
	&sadc_clk,
	&eth_clk,
	&wdt_clk,
	&gpio0_db_clk,
	&gpio1_db_clk,
	&gpio2_db_clk,
	&rgmii_tx_gate,
	&eth_rmii_gate,
	&ephy_clk_gate,
	&ac_clk,
	&i2s_clk,
	&acodec_pclk_gate,
	&ephy_pclk_gate,
	&tzpc_pclk_gate,
	&mipi0_pclk_gate,
	&mipi1_pclk_gate,
	&mipi2_pclk_gate,
	&sdc0_clk_sample,
	&sdc0_clk_drv,
	&sdc1_clk_sample,
	&sdc1_clk_drv,
	&rtc_pclk_gate,
#endif
	NULL,
};
EXPORT_SYMBOL(fh_clks);
